This invention relates to digital-to-analog converters, and more particularly, to improved interpolation circuits for use in digital-to-analog converters.
Commonly-assigned U.S. Pat. No. 5,396,245 shows a digital-to-analog converter that uses an interpolation circuit to provide an accurate analog output voltage in response to a digital control word. The digital-to-analog converter in the '245 patent divides the digital control word into two parts. The most significant subword controls the selection of a pair of voltages (V.sub.1 and V.sub.2), which bracket the desired output voltage. The least significant subword controls a bank of switches connected to an interpolation circuit that interpolates between V.sub.1 and V.sub.2 to generate the desired output voltage.
The interpolation circuit has a differential transconductance stage with inputs formed from composite transistors. Each composite transistor has a number of subtransistors. The switches selectively connect the gates of the subtransistors to either V.sub.1 or V.sub.2. The analog output voltage is increased by a given step size whenever one of the gates is switched from V.sub.1 to V.sub.2, where V.sub.2 is larger than V.sub.1. Whenever one of the gates is switched from V.sub.2 to V.sub.1, the output decreases by the same step size.
Although the interpolation circuit of the '245 patent is generally satisfactory, the interpolation voltage steps produced by that circuit are not always of precisely equal size, which can lead to error. The source of the variation in step size is the variation in transconductance of the subtransistors which occurs when some of the subtransistor gates are connected to V.sub.1 while others are connected to V.sub.2. As the subtransistor gates of some of the subtransistors are switched from V.sub.1 to V.sub.2, the gate-to-source voltages (V.sub.GS) of the unswitched subtransistors increase. This causes an increase in drain current and causes the transconductances of the unswitched subtransistors to increase. As a result of the increased transconductances of the unswitched subtransistors, when the gates of the unswitched subtransistors are subsequently switched from V.sub.1 to V.sub.2, the interpolation voltage step size is larger than it was when previous subtransistors were switched.
It is therefore an object of the present invention to provide an improved voltage interpolation circuit for a digital-to-analog converter.
It is a further object of the present invention to provide a voltage interpolation circuit that generates voltage interpolation steps of substantially equal size.